Felipe Marranghello,  Vinicius Dal Bem,  Francesc Moll,  André Reis,  Renato Ribas. 

This paper presents an extensive transistor sizing analysis for regular transistor fabrics. Several evaluation methods have been exploited, such as ring oscillators and single-gate open chain structures. Different design aspects are addressed taking into account stacked transistors and circuit critical paths. The performance degradation of using regular fabrics in comparison to standard cells is expected, but it is quite important to evaluate the dimension of such impact. The results were obtained for PTM 45nm CMOS parameters, and the conclusions can be easily extended to other technology nodes and fabrication processes.

http://www.lbd.dcc.ufmg.br/colecoes/sim/2011/005.pdf

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