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Test-Chip Structures for Local Random Variability Characterization in CMOS 65 nm

Felipe Correa WerleJuan Pablo Martinez BritoSergio Bampi

This paper describes the design of a 65nm technology test chip, aimed at investigating and characterizing the truly local random variations. The first structure is a matrix-style transistor array with closely spaced MOS transistors. The second structure comprises three arrays of ring oscillators with different numbers of stages and other two arrays of ring oscillators composed solely by single-type transistors. The third structure is based on a procedure to measure an array of stacked-pairs of identical MOS transistors. The design is done in 65nm CMOS bulk technology and the final chip area is 1580 x 1580 ?m.

http://www.lbd.dcc.ufmg.br/colecoes/sim/2011/0045.pdf

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