Synthesis and Comparison of Low-Power Architectures for SAD Calculation

Fábio WalterSergio Bampi

This paper presents the standard-cells synthesis and comparison of parallel hardware architectures for the Sum of Absolute Differences (SAD) datapath, focusing on different design points such as the tradeoff between high-performance and low-power dissipation (isoperformance target). Multi-VDD, multi-VT and different combination of parallelism and pipeline architectural techniques were explored in this work. In order to generate the results, we used the IBM 65nm standard-cells library with typical voltage of 1 V and 1.2 V, and the back-end Cadence tools, e.g. Power Analysis, for the power measurements. We achieved significant power reduction for the architectures with low-frequency and high parallelism, with High-VT and mainly with only one pipeline stage and small power source.

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