Impact of Process Variability considering Transistor Networks Delay

Jerson Paulo GuexCristina MeinhardtRicardo Reis

This paper presents an analysis of process variability considering the use of extracted layouts with their respective capacitance and parasitic resistance. The effects on PullDown and PullUp networks of transistors are verified separately. The performed experiments aimed to analyze the variability when using serial and/or parallel transistors. Also it analyzes the influence of process variability in fall delay, rise delay. Preliminary results demonstrated that both networks could be less sensitive to process variability if the network is composed by more than 2 transistors in parallel. The use of larger transistors than the minimum possible size for the used technology node also reduces the effects of variability [10].

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