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Cell-Based VLSI Implementations of the Add One Carry Select Adder

Jucemar MonteiroPedro V. CamposJosé Luís GüntzelLuciano Agostini

This paper proposes an add-one carry-select adder architecture optimized for cell-based VLSI generation. This architecture is compared to a previously proposed A1CSA architecture, as well as, to Carry-Select Adder (CSA) and Carry-Ripple Adder (CRA) architectures. Synthesis results for 45nm technology showed that, for higher order adders (32 to 256 bits), the proposed A1CSAS architecture is, on average, 13% faster than the investigated "select adders". Power and area estimates showed that, for the same range, the A1CSAS is smaller and consumes less power than the others "select adders". Power-delay results reveals that, for a bit range between 16 and 256, the A1CSAS is the most energy-efficient architecture among all investigated adders.

http://www.lbd.dcc.ufmg.br/colecoes/sim/2011/0043.pdf

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