Carlos E. Klock,  Vinicius Callegaro,  André I. Reis,  Renato P. Ribas. 

This paper presents a CAD tool to analyze switch networks and generate profiles to detect possible issues that may affect the design of integrated circuits, especially those related to routing congestion. The analysis of a switch network is useful to find out information about the general structure of the network and its layout, for instance, to predict the behavior in terms of physical area and signal routing congestion. The experimental results show that the proposed tool can identify undesired diffusion separations and possible routing congestion. Specific applications include RTL (regular transistor layout) and standard cells.

http://www.lbd.dcc.ufmg.br/colecoes/sim/2011/0027.pdf

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