V. Dal Bem,  P. F. Butzen,  F. S. Marranghello,  A. I. Reis,  R. P. Ribas. 

Regular transistor layout (RTL) is expected to reduce the process variation, increase the fabrication yield and improve the device reliability in nanometer CMOS technologies. Although the penalty in design flexibility seems to be obvious, in terms of area optimization and circuit performance, deep and extensive investigations must be done in order to evaluate the actual design cost and trade-off in using such a more lithography-aware strategy. This paper presents a detailed comparison between RTL and standard cell methodologies. Experimental results have shown that the impact of RTL technique in digital circuit design is quite manageable,presenting acceptable area overhead and even power consumption reduction for certain circuit timing constraints.

http://www.lbd.dcc.ufmg.br/colecoes/sim/2011/0013.pdf

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