Area and power Optimization of Radix-2 Decimation in Time (DIT) FFT Implementation Using MCM Approach Along the Stages

Sidinei GhissoniEduardo CostaRicardo Reis

This paper proposes the optimization of area and power of architecture radix-2 Decimation in Time (DIT) FFT using the Multiple Constant Multiplication (MCM) approach along the stages. The MCM problem has been largely applied to the reduction of the multipliers in digital filters. In MCMs, the operations over the constants are implemented by using addition/subtractions and shifts rather than the use of general multipliers. In FFT filters, the butterfly algorithm plays a central role in the complex multiplications by constants. Thus, the use of the MCM in the butterflies can reduce significantly the number of real and imaginary multiplications by constants. It can be obtained by sharing the twiddle factors of the butterflies as much as possible. In this work, we have implemented two and three stages of 16 bit-width butterfly radix-2 with decimation in time for 4 and 8-point FFT respectively, using both the MCM and gate level approaches. For each stage of the real and imaginary parts of the butterflies we are able to apply the sharing of partial coefficients using MCM. The results were obtained by synthesizing the circuits in the CADENCE Encounter RTL Compiler tool for the UMC130nm technology. The results show that reductions of 10% in area, and 7% in power are achievable when compared with the synthesis logic of the implemented behavioral unrestricted architecture.

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