Anderson Santos da Silva,  Vinicius Callegaro,  Renato P. Ribas,  André I. Reis. 

This paper presents a lookup table based method for switch networks and logic gates implementation. The proposed approach is able to deliver optimal transistor networks for all Boolean functions up to four inputs. Results show a new transistor count lower bound for P-class and NPN-class for four inputs logic gates.

http://www.lbd.dcc.ufmg.br/colecoes/sim/2011/0028.pdf

Processando consulta.