State-of-the-art CMOS circuits are sensitive to faultscaused by single event transients (SETs). Traditionally,the circuit SET propagation analysis is performed bycircuit simulation. Although very accurate, circuitsimulation demands long execution times. In this paper,we propose and evaluate an alternative method to analyzeSET propagation in CMOS logic circuits. Such methoduses a timed-logical computation, avoiding circuitsimulation. Preliminary results have shown that theproposed method is very accurate when compared toHspice simulations.
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