A high-performance multiplier is one of the most important blocks of a digital signal processor. This work describes a full custom layout design and implementation of a multiplier, which uses Booth architecture, trying to achieve a balance of area, timing, and power. The objective is to get an IP (intellectual property) for a DSP processor. The Booth architecture is based on an algorithm that reduces the number of partial products to a half when compared to the parallel array multiplier. The design flow began with a detailed study of the Booth algorithm, followed by an architecture description. After the basic blocks were defined, they were grouped hierarchically in order to structure the design. A bottom-up approach was employed and each module was tested and characterized before the upper level of design using LVS (layout versus schematic) and simulations. This circuit was developed in AMS 0.35um CMOS process using CADENCE design tools. Jorge Horacio Doorn, Gladys Kaplan, Graciela Hadad, Julio Cesar Sampaio do Prado Leite.
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