Achim Rettberg,  Mauro Zanella,  Thomas Lehmann,  Ulrich Dierkes,  Carsten Rustemeier. 

The dynamic reconfiguration of controller implementations demand a specific processing architecture. Configurable elements are for example FPGAs. The price of FPGAs is mainly determined by the pin number. This means that it is costly to realize large control systems with well-known architectures. In the case of reliable systems (e.g. steer-by-wire steering) a low pin count is not only a factor of cost but also a factor for reliability. This paper presents a new synchronous, fully re-configurable self-timed bit-serial and fully interlocked pipeline architecture called MACT. Due to bit-serial processing, bit-serial input and output systems with low pin count are required. We prove the usefulness of our architecture by an example implementation of a given problem on a Xilinx FPGA. The presented architecture is optimized for use in embedded systems to control mechatronic systems, but can be also employed in other fields of application. So we furthermore present here the pipeline architecture integration into a mechatronic design process.

http://ieeexplore.ieee.org/iel5/8726/27627/01232834.pdf?tp=&arnumber=1232834&isnumber=27627

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