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Implementing a Self-Testing 8051 Microprocessor

Erika F. CotaMargrit R. KrugMarcelo LubaszewskiLuigi CarroAltamiro A. Susin

This work presents the preliminary results obtained for the high level implementation of a self-testing 8051 microprocessor. From an existing VHDL description of the microprocessor, six main blocks were identified: a state generation block, a control unit, a validation block, an ALU, a RAM and a ROM. For five of them, a test strategy was studied and implemented, so that the whole circuit embedded test structures capable to perform the microprocessor test at-speed. In this paper, we present the test strategies used and the implementation results achieved from a synthesis process in a FPGA environment.

http://csdl.computer.org/dl/proceedings/sbcci/1999/0387/00/03870202.pdf

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