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Logic and High Level Synthesis for Communication Protocols

Ricardo N. B. LimaEmerson CarliAloysio C. P. PedrozaLuci PirmezAntônio C. de Mesquita

This work presents the results obtained using a methodology that allows the hardware implementation and the rapid prototyping of communication protocols through Logic and High Level Synthesis. The implementation results of different description styles of protocols and a comparison among the protocol implementation using the High Level Synthesis technique with standard cells library and the implementation using Programmable Logic De-vice (PLD) are presented. The results include area analysis and clock frequency evaluation of synthesized hard-ware.

http://csdl.computer.org/dl/proceedings/sbcci/1999/0387/00/03870142.pdf

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