High Speed FIR Filters for Digital Decimation

Marco BrambillaDaniele GuidiValentino Liberali

This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in mathA/D converters in sub-micron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog cross-talk.

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Biblioteca Digital Brasileira de Computação - Contato:
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