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An 9-Bit Parallel Pipelined Multiplier based on the 3-bit Recoding from Booth's Algorithm

Laércio CaldeiraTales Cleber PimentaEvandro D. C. Cotrim

This paper presents the design of a 9-bit parallel multiplier based on the Booth's Algorithm using a 3-bit recoding. Although mentioned as "possible" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.

http://csdl.computer.org/dl/proceedings/sbcci/1999/0387/00/03870088.pdf

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