An 0.25µm CMOS Injection Locked 5.6Gb/s Clock and Data Recovery Cell

Thaddeus Gabara

The harmonic clock signals in a 5.6 Gb/s NRZ (Non Return to Zero) 27 -1 pseudo-random data stream are used to injection lock a CMOS LC tank circuit to 2.8GHz. The data stream is de-serialized into two 2.8Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock. This architecture offers power savings since the data and clock rate are reduced immediately by a factor of two. A measured Bit Error Rate (BER) of less than 2E-13 at 5.6Gb/s is achieved using a conventional 0.25(m CMOS technology.

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