Alocação de Registradores a Dado de Tamanho Variável e Escalonamento de Instruções

Mariza Andrade da Silva BigonhaJosé Lucas Mourão Rangel Netto

Several superscalar processors, Intel i860, RS2000, Sparc, Motorola 88000, etc., depending on the data they represent, have different needs with respect to register size. For instance, candidates to register allocation may need register pairs to represent two halves using double precision in some instructions like load, store and moves between instructions. Thus, taking to account these facts, the problem of register allocation for this class of machines is to find an optimal register allocation, which uses a minimum number of register, that minimize spilling of live values to memory and whose scheduling graph does not have false dependence. This paper shows how to modify the Pinter's algorithm to manage the need for different size registers and using a unique data structure to represent the scheduling constrains to perform a register allocation without loosing the properties presented in the last paragraph. Clique no link abaixo para buscar o texto completo deste trabalho na Web: Buscar na Web

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