On-chip integration of a binary PPM algorithm for lossless compression of ECG: Design Space Exploration for low hardware complexity

João Janduy BrasileiroAntônio Carlos Cavalcanti

This work presents the design of a lossless data compressor specially targeted on System on Chip (SoC) implementation. It is aimed at long term digital data recording on environments with strong storage and energy limitations, with particular focus on portable ECG recorders. It is modeled using a new lossless compression method derived from the Prediction by Partial Matching (PPM) algorithm. PPM is an adaptive statistical data compression technique based on context modeling and prediction that is capable of very good compression on a variety of data. The original PPM is very resource hungry and its use results in either very slow or high power-consuming systems that are impractical for the aimed purpose, which is mobile hardware deployment. The presented system uses a binary version of the PPM algorithm. High level modeling of the implemented system was constructed and validated using electrocardiogram (ECG) signals from the ECG records MIT-BIH Arrhythmia Database. The simulation results show that the achieved compression rates (CR) are competitive in comparisonwith those obtained by other methods. Their average CR is 2.59:1, for PPM contexts from 0 to 6, and 2.46:1, for a context of 1. This condition dramatically reduces the demand for memory requirements and computational complexity, which enables easier and faster hardware implementation for portabledevices. The digital designs of the two main blocks of the compressor have been mapped to low complexity FPGA (Field Programmable Gate Array) devices. These implementations have been functionally validated with the same test benches and used for the development of an IP-Core. The corresponding time simulations have showed very promising results vis-à-vis the integration of the implemented compressor with portable complete long term data acquisition systems.

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