Evaluation of Low Power Design Techniques on an MPEG2 Video Decoder Platform

Yang JuGuido Araujo

In this paper, we discuss the design and evaluation of low-power optimization techniques on an industrial-strength MPEG-2 SoC platform. The design was performed using a TSMC90/LP (90nm) process and an ASIC Cadence tool-chain. Several power reduction techniques (clock gating, multi-threshold voltage, operand isolation and multiple supply voltage) were used to evaluate power reduction efficiency and impact on the final chip area, performance and testing. An MPEG-2 video decoder application was used as a benchmark to generate stimuli vector and switching activity. The combination of all techniques resulted in a 45% power reduction, with a 14% silicon area impact and no performance impact. Details of the methodology and relevant design issues are provided, so as to help designers pursuing their own power optimization strategies.

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