Clock Domain Crossing Check Based on Assertions - A Case Study in IP Design

Frank BehrensWalter Encinas

The current demand for complex multimillion-transistor Systems on a Chip (SoC's) usually deals with the need of multiple asynchronous clocks domains of different frequencies, either due to architectures for power optimization, or to the interface with communication protocols and/or other SoC's. The interface among these clock domains requires specific circuitry to synchronize signals launched by one clock and captured by another, in order to prevent metastability and coherence issues. There are verification tools available in the market to help the designer to check specific properties of the Clock Domain Crossing (CDC) interfaces. These tools analyze the RTL code and try to detect either reliable design structures at the interfaces, as double flip-flop synchronizers, or potential metastable signals. From the design point of view, however, there are design structures that are reliable to prevent metastability, but are not automatically detected by the current tools. This is the case for the handshake-based interface discussed in the present work. Under this assumption, CDC checking tools flag several issues on signals crossing the interface, which should be safe due to the clock domain crossing handshake. This paper presents a review of CDC fundamentals and proposes a methodology to verify clock domain crossing issues in a real, state-of-art IP, using assertion-based verification and formal verification.

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