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Automatic Translation of SysML Models to SystemC Executable Specification

Keyla BrasilDiógenes Junior

System designs become critical as implementation technology progress toward complex integrated circuits and time to-market pressure continues to grow. There is a strong necessity to develop methodologies to reduce cost and time spent during all the design phases and system development. In this paper a methodology for the automatic translation of SysML diagrams to a SystemC executable specification is proposed and demonstration of usage is shown through a case study. The proposed approach has some advantages, such as: smaller cost due to project changes, easier documentation and better understanding of the project by stake-holders.

http://www.lbd.dcc.ufmg.br/colecoes/wcas/2011/0021.pdf

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