Crístian Müller,  Paulo César C. de Aguirre,  Lucas Teixeira,  Leonardo L. de Oliveira,  João Baptista dos S. Martins. 

This paper describes the design and the test results of a full-duplex Internet Protocol Version 4 based ASIC implementation. Routing and addressing features with a re-configurable ARP table were integrated. The design was timing-driven and previous simulations have shown a 125MHz maximum operating frequency on a 0.35?m technology. The estimated statistical power consumption is 48mW. The prototyped chip has 19,060 logic equivalent cells and a total die area of 5.43mm2 . Initial tests in the prototyped integrated circuit indicate a maximum operating frequency around 50MHz, limited by the test environment constraints, but the real maximum operating frequency was estimated around 95MHz.

http://www.lbd.dcc.ufmg.br/colecoes/wcas/2011/007.pdf

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