BDBComp
Parceria:
SBC
Flávio MianaClaudionor N. Coelho Jr.Patricia NattrodtAntônio O. Fernandes

LEARN@WEB - Um Ambiente Integrado para Aprendizagem Cooperativa

We present a new technique to support processor validation and verification in obsence of information when modeling reactive systems. Current processor validation techniques will not tolerate absence of information for some of its registers. In order to overcome this problem we combine symbolic simulation with ternary logic simulation with ternary logic simulation techniques. We exemplify our techniques. We exemplify our technique by simulating an Application Specific Instruction Processor (ASIP) core with its embedded logic.

http://www.lbd.dcc.ufmg.br/colecoes/sbac-pad/1997/0017.pdf

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