49 registros retornados

• Yale Patt.  Microprocessors for the Years 2001 and 2008: Where Will We be in 2001? What Will Still Need to be Done for 2008?. 

• Enric Musoll.  Micro-Architecture Estimation of the Useless Power Consumption of a High-Performance Processor. 

• Roberto d'Amore,  Karl Heinz Kienitz,  Osamu Saotome.  A Bit Scalable Architecture for Fuzzy Processors. 

• Sergio Akira Ito,  Luigi Carro,  Ricardo Pezzuol Jacobi.  Designing a JAVA Microcontroller to Specific Applications. 

• Oscar da Costa Gouveia-Filho,  Márcio Cherem Schneider,  Carlos Galup-Montoro.  Advanced Compact Model for the Charges and Capacitances of Short-Channel MOS Transistors. 

• Jung Hyun Choi,  Sergio Bampi.  Conductances and Noise in Trapezoidal Association of Transistors for Analog Applications Using a SOT Methodology. 

• L. Miguel Silveira,  Nuno Vargas.  Multilevel Finite Difference Methods for the Characterization of Substrate Coupling in Deep Sub-Micron Designs. 

• Paulo Maciel,  Edna Barros,  Wolfgang Rosenstiel.  Estimating Functional Unit Number in the PISH Codesign System by using Petri Nets. 

• Luiza de Macedo Mourelle,  Nadia Nedjah.  Codesign System Performance based on Memory Configurations. 

• O. P. Dias,  J. Semião,  C. E. Pereira,  I. M. Teixeira,  J. P. Teixeira.  Hardware/Software Specification, Design and Test using a System Level Approach. 

• Renato P. Ribas,  Frank H. Behrens.  An Approach for Microsystems Codesign. 

• Chi-Hung Lin,  M. Ismail,  Tales C. Pimenta,  Laércio Caldeira.  A Multi-Functional Cell for CMOS Analog Applications in Low-Voltage. 

• R. L. Oliveira Pinto,  Márcio Cherem Schneider,  Carlos Galup-Montoro.  Optimum Design of MOS Amplifiers. 

• Federico Gálvez-Durand.  Odd-Order Current-Mode Lowpass Filters with Finite Zeros. 

• Cristiano C. Araújo,  Edna Barros.  An Approach for Interface Generation in the PISH Co-Design System. 

• Harri Klapuri,  Jarmo Takala,  Jukka Saarinen.  Interface Design and Refinement using State based Techniques. 

• Carlos A. Alba Pinto,  Bart Mesman,  Koen Van Eijk.  Register Files Constraint Satisfaction during Scheduling of DSP code. 

• Angel García,  Joan Vila,  Alfons Crespo,  Sergio Sáez.  A Binary-Tree Architecture for Scheduling Real-Time Systems with Hard and Soft Tasks. 

• Thaddeus Gabara.  An 0.25µm CMOS Injection Locked 5.6Gb/s Clock and Data Recovery Cell. 

• Laércio Caldeira,  Tales Cleber Pimenta,  Evandro D. C. Cotrim.  An 9-Bit Parallel Pipelined Multiplier based on the 3-bit Recoding from Booth's Algorithm. 

• José Antônio Gomes de Lima,  Elmar U. K. Melchier,  Antonio Carlos Cavalcanti.  MCA: A Single Chip One-Port Scalable ATM Layer Controller. 

• Sérgio Vale Aguiar Campos.  Symbolic Model Checking in Practice. 

• Meryem Marzouki.  Is Open Source CAD Software the Way for Innovation?. 

• Luigi Carro.  Circuit-Level Considerations for Mixed Signals Programmable Components. 

• José Vicente Calvano,  Vladimir Castro Alves,  Marcelo Lubaszewski.  ault Detection in Systems with 2 nd Order Dynamics using Transient Analysis. 

• Jorge M. Cañive,  José Gabriel R. C. Gomes,  Antonio Petraglia.  A Low Sensitivity Switched-Capacitor Filter Design with Testability Features. 

• Ana C. V. de Melo.  Reusing Hardware Components with Single-State Processes. 

• Marco Brambilla,  Daniele Guidi,  Valentino Liberali.  High Speed FIR Filters for Digital Decimation. 

• Denis Franco,  Luigi Carro.  An FPGA Version of a Non-Linear Adaptive Filter. 

• José C. Monteiro.  Power Optimization using Dynamic Power Management. 

• Ricardo N. B. Lima,  Emerson Carli,  Aloysio C. P. Pedroza,  Luci Pirmez,  Antônio C. de Mesquita.  Logic and High Level Synthesis for Communication Protocols. 

• L. Carro,  M. Kreutz,  F. Wagner,  M. Oyamada.  System Synthesis and Processor Selection in the S3E2S Environment

• Joco M. P. Cardoso,  Horacio C. Neto.  Fast Hardware Compilation of Behaviors into an FPGA-based Dynamic Reconfigurable Computing Systems. 

• I. Skliarova,  A. B. Ferrari.  An Architect's Workbench for Reconfigurable Computing. 

• M. Renovell,  F. Azaïs,  Y. Bertrand.  Test Escapes: Analysis of Short Defect. 

• R. Velazco,  Ph. Cheynet,  R. Ecoffet.  Effects of Radiation on Digital Architectures: One Year Results from a Satellite Experiment. 

• Fabian Vargas,  Michael Nicolaidis.  Criteria for Static Current Estimation: How Good are They? An Approach Incorporating IC Quality Requirements. 

• Janor A. Bastos,  Jáder A. Kussler,  Leandro J. Cassol,  Marcelo S. Lubaszewski.  On-Line Testing of a Switching Circuit. 

• André Inácio Reis.  Covering Strategies for Library Free Technology Mapping. 

• Fernanda Gusmão de Lima,  Marcelo de O. Johann,  José Luís Güntzel,  Luigi Carro,  Ricardo Reis.  A Tool for Analysis of Universal Logic Gates Functionality. 

• Leandro Soares Indrusiak,  Ricardo Augusto da Luz Reis.  Project Management and Design Methodology Support for the CAVE Project: A Hyperdocument-Centric Approach. 

• João P. Marques-Silva,  Luís Guerra e Silva.  Solving Satisfiability in Combinational Circuits with Bactrack Search and Recursive Learning. 

• Paulo Sérgio Cardoso,  Marius Strum,  José Roberto de A. Amazonas,  Wang Jiang Chau.  Comparison between Quasi-Uniform Linear Cellular Automata and Linear Feedback Shift Registers as Test Pattern Generators for Built-in Self-Test Applications. 

• Erika F. Cota,  Margrit R. Krug,  Marcelo Lubaszewski,  Luigi Carro,  Altamiro A. Susin.  Implementing a Self-Testing 8051 Microprocessor. 

• Peter Bukovjan,  Meryem Marzouki,  Walid Maroufi.  Design for Testability Reuse in Synthesis for Testability. 

• Serafín Olcoz.  Semiconductor Knowledge Management and Soft-Cores Reuse. 

• João Fragoso,  Eduardo Costa,  Juergen Rochol,  Sergio Bampi,  Ricardo Reis.  Specification and Design of an Ethernet Interface Soft IP. 

• Sérgio L. C. Salomão,  M. S. de Alcântara,  Vladimir C. Alves,  Antônio C. C. Vieira.  SCOB, A Soft-Core for the Blowfish Cryptographic Algorithm. 

• Yervant Zorian.  Testing Semiconductor Chips: Trends and Solutions.