45 registros retornados

• Samuel Nascimento Pagliarini,  Fernanda Lima Kastensmidt.  VEasy: a Functional Verification Tool Suite.  13 - 16

• Gracieli Posser,  Guilherme Flach,  Gustavo Wilke,  Ricardo Reis.  Gate Sizing Minimizing Delay and Power/Area.  17 - 22

• Paulo A. Haacke,  Samuel N. Pagliarini,  Fernanda L. Kastensmidt.  Evaluating Stimuli Generation Using the VEasy Functional Verification Tool Suite.  23 - 26

• Gerson Scartezzini,  Ricardo Reis.  Using Transistor Networks to Reduce Static Power in CMOS Circuits.  27 - 30

• Felipe Marranghello,  Vinicius Dal Bem,  Francesc Moll,  André Reis,  Renato Ribas.  Transistor Sizing Analysis of Regular Fabrics.  31 - 34

• Mayler G. A. Martins,  Vinicius Callegaro,  Renato P. Ribas,  André I. Reis.  Computing Minimum Decision Chains of Boolean Functions.  35 - 38

• Eduarda R. Monteiro,  Bruno B. Vizzotto,  Cláudio M. Diniz,  Bruno Zatt,  Sergio Bampi.  Multiprocessing Acceleration of H.264/AVC Motion Estimation Full Search Algorithm under CUDA Architecture.  41 - 44

• Fábio Walter,  Sergio Bampi.  Synthesis and Comparison of Low-Power Architectures for SAD Calculation.  45 - 48

• Gustavo Sanchez,  Diego Noble,  Marcelo Porto,  Sergio Bampi,  Luciano Agostini.  A Real Time HDTV Motion Estimation Architecture for the New MPDS Algorithm.  49 - 52

• Mateus Grellert,  Felipe Sampaio,  Julio C. B. Mattos,  Luciano Agostini.  Multilevel Data Reuse Scheme for Off-Chip Memory Accesses Reduction Applied to a Motion Estimation Architecture.  53 - 56

• Daniel Palomino,  Guilherme Corrêa,  Luciano Agostini,  Altamiro Susin.  Fast Distortion-Based Heuristic and Hardware Design for the H.264/AVC Intra-Frame Decision.  57 - 60

• Felipe Sampaio,  Bruno Zatt,  Sergio Bampi,  Luciano Agostini.  Data Reuse Scheme for an Out-of-Order Motion and Disparity Estimation Targeting the Multiview Video Coding.  61 - 64

• V. Dal Bem,  P. F. Butzen,  F. S. Marranghello,  A. I. Reis,  R. P. Ribas.  Area Overhead and Performance Impact of Regular Transistor Layout Design in Digital Integrated Circuit.  67 - 70

• Walter Calienes Bartra,  Fernanda G. de Lima Kastensmidt,  Ricardo Reis.  SET and SEU Simulation Toolkit for LabVIEW.  71 - 74

• Guilherme Flach,  Marcelo Johann,  Ricardo Reis.  Prematurely Aborting Linear System Solver in Quadratic Placement.  75 - 78

• Vinícius N. Possani,  Luciano V. Agostini,  Felipe S. Marques,  Leomar S. da Rosa Jr..  Decreasing Transistor Count Using an Edges Sharing Technique in a Graph Structure.  79 - 82

• Érico de Morais Nunes,  Reginaldo da Nóbrega Tavares.  Sroute: A Router Tool for Structured ASICs.  83 - 86

• Julio S. Domingues Jr.,  Renato S. de Souza,  Vinicius N. Possani,  Felipe S. Marques,  Leomar S. da Rosa Jr..  An Algorithm for Generating Logical Expressions Using a Graph-based Approach.  87 - 90

• Jean F. G. Quadro,  Tiago H. Trojahn,  Juliano L. Gonçalves,  Luciano V. Agostini,  Leomar S. da Rosa Junior.  A Media Processing Implementation for ISDTV Middleware with Optional Hardware Acceleration Support.  93 - 96

• Cássio Cristani,  Pargles Dall'Oglio,  Diego Noble,  Marcelo Porto,  Luciano Agostini,  Sérgio Bampi.  Random Search Motion Estimation Algorithm for High Definition Videos.  97 - 100

• Alonso A. de A. Schmidt,  Altamiro A. Susin.  CABAC Integration Into an H.264/AVC Intra-only Hardware Video Decoder.  101 - 104

• Marcel Moscarelli Corrêa,  Mateus Thurow Schoenknecht,  Luciano Volcan Agostini.  A High Throughput Hardware Solution for the H.264/AVC Quarter-Pixel Motion Estimation Refinement.  105 - 108

• Bruno George de Moraes,  Ismael Seidel,  José Luís A. Güntzel.  A Rate-Distortion Metric Targeting Perceptual Video Coding.  109 - 112

• Jeffrei Moreira,  Jônatas Rech,  Henrique Klein,  Altamiro Susin.  Processor and Demux Integration for the SoC-SBTVD.  113 - 116

• Guilherme Flach,  Marcelo Johann,  Lucas Nunes,  Ricardo Reis.  On Placement Coloring.  119 - 122

• Kim A. Escobar,  Paulo F. Butzen,  André I. Reis,  Renato P. Ribas.  A Test Environment for Validation of Subthreshold and Leakage Current Estimation Method in CMOS Logic Gates.  123 - 126

• Carlos E. Klock,  Vinicius Callegaro,  André I. Reis,  Renato P. Ribas.  CAD Tool for Switch Network Profiling.  127 - 130

• Anderson Santos da Silva,  Vinicius Callegaro,  Renato P. Ribas,  André I. Reis.  A Lookup Table Method for Optimal Transistor Network Synthesis.  131 - 134

• Thiago Raupp da Rosa,  Douglas Cardoso,  Fernando Moraes.  A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCs.  137 - 140

• Sandro Ferreira,  Everton Ghignatti,  Alcides Costa,  Eric Fabris.  Analog Design Methodology adopted in Training Center 1.  141 - 144

• Tales M. Chaves,  Fernando G. Moraes.  Energy-efficient Cache Coherence Protocol for NoC-based MPSoCs.  145 - 148

• Paulo César C. de Aguirre,  Felipe C. Lucchese,  Lucas Teixeira,  Crístian Müller,  César Augusto Prior.  Digital Logic Cancellation Block for a Cascade Feed-Forward Sigma-Delta Analog-to-Digital Converter.  149 - 152

• Paulo Santos,  Jonathan Martinelli,  Cezar Reinbrecht,  Débora Matos,  Altamiro Susin.  Efficient Processing Element Unit for MPSoC NoC-based.  153 - 156

• Jorge Tonfat,  Ricardo Reis.  Design and Verification of a Layer-2 Ethernet MAC Classification Engine for a Gigabit Ethernet Switch.  159 - 162

• Jorge Tonfat,  Gustavo Neuberger,  Ricardo Reis.  Functional Verification of logic modules for a Gigabit Ethernet Switch.  163 - 166

• Ilan Correa,  José Luís Güntzel,  Aldebaro Klautau,  João Crisóstomo Costa.  A Direct Memory Access Controller (DMAC) IP-Core using the AMBA AXI protocol.  167 - 172

• Abilio G. Parada,  Eliane Siegert,  Lisane B. de Brisolara.  GenCode: A tool for generation of Java code from UML class models.  173 - 176

• Stephan Hermes Chagas,  Leonardo Londero de Oliveira,  João Baptista S. Martins.  Review of Localization Schemes Using Artificial Neural Networks in Wireless Sensor Networks.  177 - 180

• Bruno Hecktheuer,  Eduardo Nicola,  Mateus Grellert,  Júlio C. B. Mattos.  Power Analysis of a Floating Point Unit for a Reconfigurable Architecture.  181 - 184

• Jerson Paulo Guex,  Cristina Meinhardt,  Ricardo Reis.  Impact of Process Variability considering Transistor Networks Delay.  187 - 190

• Sidinei Ghissoni,  Eduardo Costa,  Ricardo Reis.  Area and power Optimization of Radix-2 Decimation in Time (DIT) FFT Implementation Using MCM Approach Along the Stages.  191 - 196

• Renê A. Benvenuti,  Adriano Renner,  Altamiro A. Susin.  Development of the Overlap and Add Block for SoC-SBTVD Audio MPEG4-AAC Decoder and Hardware Interface with the wm8731 CoDec.  197 - 200

• Jucemar Monteiro,  Pedro V. Campos,  José Luís Güntzel,  Luciano Agostini.  Cell-Based VLSI Implementations of the Add One Carry Select Adder.  201 - 204

• Raphael A. Camponogara Viera,  Paulo César C. de Aguirre,  Leonardo Londero de Oliveira,  João Baptista Martins.  Iterative Mode Hardware Implementation of CORDIC Algorithm.  205 - 208

• Felipe Correa Werle,  Juan Pablo Martinez Brito,  Sergio Bampi.  Test-Chip Structures for Local Random Variability Characterization in CMOS 65 nm.  209 - 214