58 registros retornados

• Grant Martin.  SystemC: From Language to Applications, from Tools to Methodologies. 

• Patrick Lysaght.  System-Level Design for FPGAs. 

• Luiz Franca-Neto.  High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package. 

• Julio Arlindo Pinto Azevedo,  Tales Cleber Pimenta.  Design of a Low Noise Amplifier for CDMA Transceivers at 900MHz in CMOS 0.35 µm. 

• Elkim Roa,  Joao Navarro Soares,  Wilhelmus Van Noije.  A Methodology for CMOS Low Noise Ampli.er Design. 

• Pablo Aguirre,  Fernando Silveira.  Design of a Reusable Rail-to-Rail Operational Amplifier. 

• S. P. Gimenez,  M. A. Pavanello,  J. A. Martino,  S. Adriaensen,  D. Flandre.  Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. 

• Maurizio Damiani,  Andrei Y. Selchenko.  Boolean Technology Mapping Based on Logic Decomposition. 

• Ivan Augé,  François Donnet,  Frédéric Pétrot.  Retiming Finite State Machines to Control Hardened Data-Paths. 

• Luca P. Carloni,  Alberto L. Sangiovanni-Vincentelli.  Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits. 

• Dmitri Maslov,  Gerhard W. Dueck,  D. Michael Miller.  Simplification of Toffoli Networks via Templates. 

• Grant Martin.  SystemC and the Future of Design Languages: Opportunities for Users and Research. 

• Eduardo Costa,  Sergio Bampi,  Jose Monteiro.  A New Pipelined Array Architecture for Signed Multiplication. 

• Sumeer Goel,  Mohamed A. Elgamel,  Magdy A. Bayoumi.  Novel Design Methodology for High-Performance XOR-XNOR Circuit Design. 

• Achim Rettberg,  Florian Dittmann,  Mauro Zanella,  Thomas Lehmann.  Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. 

• Mario P. Vestias,  Horacio C. Neto.  DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. 

• Diogo Zandonai,  Sergio Bampi,  Marcel Bergerman.  ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA. 

• Abel Guilhermino da S. Filho,  Alejandro C. Frery,  Cristiano Coelho de Araujo,  Haglay Alice,  Jorge Cerqueira,  Juliana A. Loureiro,  Manoel Eusebio de Lima,  Maria das Gracas S. Oliveira,  Michelle Matos Horta.  Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm. 

• Sandro Ferreira,  Felipe Haffner,  Luis Fernando Pereira,  Fernando Moraes.  Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs. 

• Nadia Nedjah,  Luiza de Macedo Mourelle.  FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic. 

• Markus Visarius,  Johannes Lessmann,  Wolfram Hardt,  Frank Kelso,  Wolfgang Thronicke.  An XML Format Based Integration Infrastructure for IP Based Design. 

• Uilian R. F. Souza,  Sperb Sperb,  Braulio A. de Mello,  Flavio R. Wagner.  Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment. 

• Julio A. de Oliveira Filho,  Manoel Eusébio de Lima,  Paulo Romero Maciel,  Juliana Moura,  Bruno Celso.  A Fast IP-Core Integration Methodology for SoC Design. 

• Eric E. Fabris,  Luigi Carro,  Sergio Bampi.  A Universal High-Performance Analog Interface for Signal Processing SOCs. 

• Santanu Dutta.  Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems. 

• Joao Fragoso,  Gilles Sicard,  Marc Renaudin.  Automatic Generation of 1-of-M QDI Asynchronous Adders. 

• Artur Pereira,  Antonio Rui Borges,  Antonio Ferrari.  Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits. 

• Tang Lei,  Shashi Kumar.  Algorithms and Tools for Network on Chip Based System Design. 

• Cesar Albenes Zeferino,  Altamiro Amadeu Susin.  SoCIN: A Parametric and Scalable Network-on-Chip. 

• J. Soldera,  A. Vilas Boas,  A. Olmos.  A Low Ripple Fully Integrated Charge Pump Regulator. 

• A. Olmos.  A Temperature Compensated Fully Trimmable On-Chip IC Oscillator. 

• Fernando C. Castaldo,  Joao Paulo C. Cajueiro,  Carlos Alberto dos Reis.  Bias Dependence of Noise Correlation in MAGFETs.  Buscar na Web Processando consulta.

• Esther O. Rodríguez-Villegas,  Alberto Yúfera,  Adoración Rueda.  A Charge Correction Cell for FGMOS-Based Circuits. 

• Renato E. B. Poli,  Felipe R. Schneider,  Renato P. Ribas,  André I. Reis.  Unified Theory to Build Cell-Level Transistor Networks from BDDs. 

• Mauricio Ayala-Rincon,  Rodrigo B. Nogueira,  Carlos H. Llanos,  Ricardo P. Jacobi,  Reiner W. Hartenstein.  Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. 

• G. Logothetis,  K. Schneider,  C. Metzler.  Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification. 

• Geert Janssen.  A Consumer Report on BDD Packages. 

• Arnold Azevedo,  Rodrigo Soares,  Ivan Saraiva Silva.  A New Hybrid Parallel/Reconfigurable Architecture:The X4CP32. 

• Achim Rettberg,  Mauro Zanella,  Thomas Lehmann,  Ulrich Dierkes,  Carsten Rustemeier.  Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture. 

• Juergen Becker,  Alexander Thomas,  Maik Scheer.  Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. 

• Ryuichi Takahashi,  Hajime Ohiwa.  Situated Learning on FPGA for Superscalar Microprocessor Design Education. 

• Howard H. Chen,  J. Scott Neely,  Michael F. Wang,  Gricel Co.  On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction. 

• Mohamed A. Elgamel,  Magdy A. Bayoumi.  Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction. 

• Janet Meiling Wang,  Pinhong Chen,  Omar Hafiz.  A New Continuous Switching Window Computation with Crosstalk Noise. 

• Renato Fernandes Hentschke,  Ricardo Augusto da Luz Reis.  Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. 

• Patrick Lysaght.  Future Design Tools for Platform FPGAs. 

• Juergen Becker,  Michael Huebner,  Michael Ullmann.  Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. 

• Romanelli Lodron Zuim,  Claudionor J. Nunes Coelho Júnior,  Luiz Fernando Etrusco Moreira,  Antônio Otávio Fernandes,  José Monteiro da Mata,  Diógenes Cecílio da Silva Jr..  Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs. 

• Daniel Ferrão,  Gustavo Wilke,  Ricardo Reis,  José Luís Güntzel.  Improving Critical Path Identification in Functional Timing Analysis. 

• Cristiano Santos,  Gustavo Wilke,  Cristiano Lazzari,  Ricardo Reis,  José Luís Güntzel.  A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. 

• Alessandro Girardi,  Fernando Paixao Cortes,  Eric Fabris,  Sergio Bampi.  Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology. 

• Antonio J. Ginés,  Eduardo J. Peralías,  Adoración Rueda.  Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. 

• Faress Tissafi-Drissi,  Ian O'Connor,  Fabien Mieyeville,  Frederic Gaffiot.  Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends. 

• Marcelo Negreiros,  Erik Schuler,  Luigi Carro,  Altamiro A. Susin.  Testing RF Signal Paths Using Spectral Analysis and Subsampling. 

• J. Perez,  M. Sonza Reorda,  M. Violante.  Accurate Dependability Analysis of CAN-Based Networked Systems. 

• Christian Haubelt,  Dirk Koch,  Jurgen Teich.  ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. 

• Antonio C. S. Beck Filho,  Julio C. B. Mattos,  Flavio R. Wagner,  Luigi Carro.  CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator. 

• Ney Calazans,  Edson Moreno,  Fabiano Hessel,  Vitor Rosa,  Fernando Moraes,  Everton Carara.  From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.