M. Hübner,
T. Becker,
J. Becker.
Real-time LUT-based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration. 
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A. Vilas Boas,
J. Soldera,
A. Olmos.
A 1.8V Multi-Frequency Digitally Trimmable On-Chip IC Oscillator with Low Voltage Detection Capability. 
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K. Danne.
Distributed Arithmetic FPGA Design with Online Scalable Size and Performance. 
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A. Thomas,
T. Zander,
J. Becker.
Adaptive DMA-based I/O Interfaces for Data Stream Handling in Multigrained Reconfigurable - Hardware Architectures. 
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H. D. Wohlmuth,
D. Kehrer.
A Low Power 13Gb/s 2^7-1 Pseudo Random Bit Sequence Generator IC in 120nm Bulk CMOSH.-D.. 
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Ch. Meise,
Ch. Grimm.
A SystemC Based Case Study of a Sensor Application using the BeCom Modeling Methodology for Virtual Prototyping. 
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