BDBComp - Biblioteca Digital Brasileira de Computação

XVII Symposium on Integrated Circuits and Systems Design - 2004 - Porto de Galinhas, PE, Brasil

51 registros retornados

E. Carvalho, N. Calazans, E. Brião, F. Moraes. PADReH - A Framework for the Design and Implementation of Dynamically and Partially Reconfigurable Systems. Buscar na Web Processando consulta.
P. S. B. Nascimento, P. R. M. Maciel, M. E. Lima, R. E. Sant'ana, A. G. da Silva Filho. A Partial Reconfigurable Architecture for Controllers based on Petri Nets. Buscar na Web Processando consulta.
A. Ahmadinia, C. Bobda, D. Koch, M. Majer, J. Teich. Task Scheduling for Heterogeneous Reconfigurable Computers. Buscar na Web Processando consulta.
M. Hübner, T. Becker, J. Becker. Real-time LUT-based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration. Buscar na Web Processando consulta.
H. Klimach, A. Arnaud, M. C. Sctitulohneider, C. Galup-Montoro. Characterization of MOS Transistor Current Mismatch. Buscar na Web Processando consulta.
J. Cañive, A. Petraglia, M. R. Petraglia. A 0.8 um CMOS Switched-Capacitor Filter for Video Frequency Applications. Buscar na Web Processando consulta.
A. Vilas Boas, J. Soldera, A. Olmos. A 1.8V Multi-Frequency Digitally Trimmable On-Chip IC Oscillator with Low Voltage Detection Capability. Buscar na Web Processando consulta.
E. E. Fabris, L. Carro, S. Bampi. Modeling and Designing High Performance Analog Reconfigurable Circuits. Buscar na Web Processando consulta.
F. C. Sica, C. N. Coelho Júnior, J. A. Nacif. Exception Handling in Microprocessors Using Assertion Libraries. Buscar na Web Processando consulta.
G. Al Sammane, J. Schmaltz, D. Toma, P. Ostier, D. Borrione. TheoSim: Combining Symbolic Simulation and Theorem Proving for Hardware Verification. Buscar na Web Processando consulta.
K. R. G. da Silva, E. U. K. Melcher, G. C. S. de Araujo, V. A. Pimenta. An Automatic Testbench Generation Tool for a SystemC Functional Verification Methodology. Buscar na Web Processando consulta.
F. Corno, J. P. Acle, M. S. Reorda, M. Violante. A Multi-level Approach to the Dependability Analysis of Networked Systems Based on the CAN Protocol. Buscar na Web Processando consulta.
J. V. do Vale Neto. Design Sequence for a LC-tank Voltage Controlled Oscillator in CMOS for RF. Buscar na Web Processando consulta.
V. H. V. Baroncini, O. C. Gouveia-Filho. Design of RF CMOS Low Noise Amplifiers Using a Current Based MOSFET Model. Buscar na Web Processando consulta.
C. P. Moreira, A. A. Shirakawa, E. Kerherve, P. Jarry, D. Belot. Dual-Mode RF Receiver Front-End Using a 0.25-mm 60-GHz fT SiGe:C BiCMOS7RF Technology. Buscar na Web Processando consulta.
F. P. H. Miranda, J. Navarro S. Jr.. A 4 GHZ Dual Modulus divide-by 32/32 Prescaler in 0.35Âµm CMOS Technology. Buscar na Web Processando consulta.
C. E. Savioli, C. C. Szendrodi, J. V. Calvano, A. C. de Mesquita Filho. ATPG for Fault Diagnosis on Analog Electrical Networks Using Evolutionary Techniques. Buscar na Web Processando consulta.
E. F. Cota, M. Negreiros, M. S. Lubaszewski, A. Andrade Jr.. Improving Mixed-Signal SOC Testing: a Power-aware Reuse-based Approach with Analog BIST. Buscar na Web Processando consulta.
A. M. Amory, E. F. Cota, M. S. Lubaszewski, F. G. Moraes. Reducing Test Time with Processor Reuse in NoC-Based Systems. Buscar na Web Processando consulta.
T. Murgan, C. Schlachta, L. Indrusiak, M. Glesner, R. Reis. Accurate Capture of Timing Parameters in On-Chip Interconnects. Buscar na Web Processando consulta.
J. M. S. Silva, L. M. Silveira. Issues in Parallelizing Multigrid-Based Substrate Model Extraction and Analysis. Buscar na Web Processando consulta.
G. Trucco, G. Boselli, Valentino Liberali. An Approach to Computer Simulation of Bonding and Package Crosstalk in Mixed-Signal CMOS ICs. Buscar na Web Processando consulta.
K. Danne. Distributed Arithmetic FPGA Design with Online Scalable Size and Performance. Buscar na Web Processando consulta.
A. Thomas, T. Zander, J. Becker. Adaptive DMA-based I/O Interfaces for Data Stream Handling in Multigrained Reconfigurable - Hardware Architectures. Buscar na Web Processando consulta.
E. M. Camacho-Galeano, C. Galup-Montoro, M. C. Schneider. An Ultra-Low-Power Self-Biased Current Reference. Buscar na Web Processando consulta.
A. Arnaud, C. Galup-Montoro. A Fully Integrated Physical Activity Sensing Circuit for Implantable Pacemakers. Buscar na Web Processando consulta.
A. C. S. Beck Filho, L. Carro. A VLIW Low Power Java Processor for Embedded Applications. Buscar na Web Processando consulta.
R. Barreto, M. Oliveira Júnior, M. Neves, P. Maciel. A Formal Software Synthesis Approach for Embedded Hard Real-Time Systems. Buscar na Web Processando consulta.
L. B. Becker, M. A. Wehrmeister, C. E. Pereira. Power and Performance Tuning in the Synthesis of Real-Time Scheduling Algorithms for Embedded Applications. Buscar na Web Processando consulta.
F. Zschornack, M. S. Oyamada, F. R. Wagner. Accurate Software Performance Estimation Using Domain Classification and Neural Networks. Buscar na Web Processando consulta.
M. C. B. Osorio, C. A. Sampaio, A. I. Reis, R. P. Ribas. Enhanced 32-bit Carry Lookahead Adder using Multiple Output Enable-Disable CMOS Differential Logic. Buscar na Web Processando consulta.
M. Leong, P. Vasconcelos, J. R. Fernandes, L. Sousa. A Programmable Cellular Neural Network Circuit. Buscar na Web Processando consulta.
T. Vogt, N. Wehn, P. Alves. A Multi-standard Channel-decoder for Base-station Applications. Buscar na Web Processando consulta.
M. J. Thul, N. Wehn. FPGA Implementation of Parallel Turbo Decoders. Buscar na Web Processando consulta.
C. A. Zeferino, F. G. M. do Espírito Santo, A. A. Susin. ParIS: A Parameterizable Interconnect Switch for Networks-on-Chip. Buscar na Web Processando consulta.
P. Zipf, H. Hinkelmann, A. Ashraf, M. Glesner. A Switch Architecture and Signal Synchronization for GALS System-on-Chips. Buscar na Web Processando consulta.
R. Soares, I. S. Silva, A. Pereira. When Reconfigurable Architecture Meets Network on Chip. Buscar na Web Processando consulta.
M. Jacomet, J. Goette, V. Zbinden, C. Narvaez. On the Dynamic Behavior of a Novel Digital-Only Sigma-Delta A/D Converter. Buscar na Web Processando consulta.
D. Camarero de la Rosa, J. F. Naviner, P. Loumeau. Background and Blind Calibration for Clock Skew Error in Time-Interleaved Analog-to-Digital Converters. Buscar na Web Processando consulta.
H. D. Wohlmuth, D. Kehrer. A Low Power 13Gb/s 2^7-1 Pseudo Random Bit Sequence Generator IC in 120nm Bulk CMOSH.-D.. Buscar na Web Processando consulta.
V. Rosa, S. Bampi, E. Costa, J. Monteiro. An Improved Synthesis Method for Low Power Hardwired FIR Filters. Buscar na Web Processando consulta.
Ch. Meise, Ch. Grimm. A SystemC Based Case Study of a Sensor Application using the BeCom Modeling Methodology for Virtual Prototyping. Buscar na Web Processando consulta.
M. Ayala-Rincon, R. P. Jacobi, L. G. A. Carvalho, C. Llanos, R. W. Hartenstein. Modeling and Prototyping Dynamically Reconfigurable Systems for Efficient Computation of Dynamic Programming Methods. Buscar na Web Processando consulta.
V. P. Correia, A. I. Reis. Advanced Technology Mapping for Standard-Cell Generators. Buscar na Web Processando consulta.
F. Hamzaoglu, D. Garrett, M. R. Stan. Non-Manhattan Maze Routing. Buscar na Web Processando consulta.
L. A. P. Melek, M. C. Schneider, C. Galup-Montoro. Body-Bias Compensation Technique for Subthreshold CMOS Static Logic Gates. Buscar na Web Processando consulta.
Y. S. Dhillon, A. U. Diril, A. Chatterjee, A. D. Singh. Low-Power Dual Vth Pseudo Dual Vdd Domino Circuits. Buscar na Web Processando consulta.
F. Sill, F. Grassert, D. Timmermann. Low Power Gate-level Design with Mixed-Vth (MVT) Techniques. Buscar na Web Processando consulta.
Enrico Macii. Leakage Power Optimization in Standard-Cell Designs. Buscar na Web Processando consulta.
Mike Hutton. Advances and Trends in FPGA Design. Buscar na Web Processando consulta.
César Augusto Dueñas. Verification and Test Challenges in SoC Designs. Buscar na Web Processando consulta.