52 registros retornados

• C. Coelho Jr.,  D. da Silva Jr.,  A. Fernandes.  Hardware-Software Codesign of Embedded Systems

• R. Velazco.  The ALFA-HUERTA Project

• S. Haynes,  A. Ferrari,  P. Cheung.  Algorithms and Structures for Reconfigurable Multiplication Units

• F. França,  V. Alves,  C. Amorim,  L. Malter.  Reconfigurable Hardware for Tomographic Processing

• J. Becker,  A. Kirschbaum,  F. Renner,  M. Glesner.  Internet-based Training of Reconfigurable Technologies

• R. Reis,  L. Indrusiak.  Microelectronics Education using WWW and CAD Tools

• A. Araújo,  A. Fernandes,  R. Tavares,  C. Coelho Jr..  Implementation of an Edge Detection Algorithm in a Reconfigurable Computing System

• Ernesto Damiani,  Andrea G. B. Tettamanzi,  Valentino Liberali.  Automatic Synthesis of Hashing Function Circuits using Evolutionary Techniques. 

• V. Sklyarov,  N. Lau,  A. Oliveira,  A. Melo,  K. Kondratjuk,  A. Ferrari,  R. Monteiro,  I. Skliarova.  Synthesis Tools and Design Environment for Dynamically Reconfigurable FPGAs

• R. Ubar,  D. Borrione.  Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model

• F. Vargas,  E. Bezerra,  A. Terroso,  D. Barros Jr..  Reliability Verification of Fault-Tolerant Systems Design based on Mutation Analysis

• José Roberto de A. Amazonas,  Marius Strum,  Wang Jiang Chau.  Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case. 

• M. Glesner,  A. Kirschbaum.  State-of-the-Art in Rapid Prototyping

• M. Renovell.  SRAM-based FPGAs: A Structural Test Approach

• J. Cura,  D. Santos.  A Novel 12-Bit, 3(s, Integrating-Type CMOS Analog-to-Digital Converter

• O. Calvo,  M. González,  C. Romero,  E. García-Moreno,  E. Isern,  M. Roca,  J. Segura.  Integrated Cmos Linear Dosimeter. 

• Rui L. Aguiar.  A Physical Layer Controller for Wireless Infrared Networks

• D. Archambaud,  P. Gaglione.  A Versatile, Low-Power Platform for PHS Silicon Integration

• Vanderlei Moraes Rodrigues,  Flavio Rech Wagner.  A Temporal Logic for Data-Flow VHDL

• D. Déharbe,  S. Shankar,  E. Clarke.  Formal Verification of VHDL ¾ The Model Checker CV

• D. Borrione,  J. Dushina,  L. Pierre.  Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis

• E. Garcez,  W. Rosenstiel.  CVF ¾ Coverification Framework

• J. Cobo,  W. Van Noije.  VHDL Models for High Level Synthesis of Fuzzy Logic Controllers

• F. do Nascimento,  W. Rosenstiel.  A Co-Synthesis Approach based on Symbolic Reachability Analysis

• L. Indrusiak,  R. Reis.  A Case Study for a WWW based CAD Framework

• R. Brannen,  H. Elwan,  M. Ismail.  Linear MOSFET-C Integrators using a Single Triode Region MOS Resistance

• R. Zebulum,  M. Pacheco,  M. Vellasco.  Synthesis of CMOS Operational Amplifiers through Genetic Algorithms

• F. A. P. Barúqui,  A. Petraglia,  S. Mitra,  J. E. Franca.  Efficient IC Design of SC Decimation Filters

• H. Singh,  M. Lee,  G. Lu,  F. Kurdahi,  N. Bagherzadeh.  MorphoSys: A Reconfigurable Architecture for Multimedia Applications

• Franco Maloberti,  Valentino Liberali,  Piero Malcovati.  Signal Processing for Smart Sensors. 

• J. Alcântara,  V. C. Alves,  E. Filho.  Designing the Dispatch Stage of a Superscalar Microprocessor

• J. S. Aude,  M. T. Young,  G. Bronstein.  A High-Performance Switching Element for a Multistage Interconnection Network. 

• S. Salomão,  V. Alves,  E. Filho.  A Two-level Pipelined Implementation of the IDEA Cryptographic Algorithm

• R. Velazco,  P. Cheynet,  R. Ecoffet.  Operation in Space of Artificial Neural Networks Implemented by Means of a Dedicated Architecture based on a Transputer

• Gabriel Parmegianni Jahn,  Luigi Carro.  A Non-Linear Adaptive Filter for Sensor and Amplifier Linearization

• Oscar Calvo,  Miquel Roca.  Low-Power Fully-Testable Flow Meter in CMOS ASIC. 

• F. Azaïs,  Y. Bertrand,  S. Mir,  M. Renovell,  M. Lubaszewski.  A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing

• A. Sarmiento-Reyes,  M. Gutierrez-de Anda,  V. Champac.  A Graph-Oriented CAD Tool for Establishing the Topological Diagnostic Conditions of Analogue Circuits

• M. Marzouki.  France-Brazil Cooperative Actions

• F. Salazar,  J. Pimentel,  M. Pacheco,  M. Vellasco.  Micro Power CMOS Analog Cells. 

• T. Tarim,  M. Ismail,  H. Kuntman.  Statistical Design of a Multiplier using a Low Power Square-Law CMOS Analog Cell

• C. Lin,  T. Pimenta,  M. Ismail.  A Low-Voltage CMOS Exponential Function Circuit for AGC Applications

• J. López,  R. Sarmiento,  R. Reina,  E. Charry.  Circuits for Low Power Consumption in GaAs Technology

• J. Güntzel,  M. Johann,  L. Carro,  F. Gusmao de Lima,  R. Reis.  Improving Logic Density of QCL Masterslices by using Universal Logic Gates

• J. Güntzel,  A. Pinto,  R. Reis,  F. Moraes.  An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays

• A. Reis,  R. Reis,  M. Robert.  Topological Parameters for Library Free Technology Mapping

• R. Jacobi.  LogosPGA: Synthesis System for LUT Devices

• V. Sklyarov.  Logic Synthesis of Reconfigurable Control Circuits based on Mutually Exclusive Reprogrammable Elements

• S. Muddu,  E. Sarto,  M. Hofmann,  A. Bashteen.  Repeater and Interconnect Strategies for High-Performance Physical Designs

• M. Vaz,  R. Natalizi.  A Tool to Design Circuits with Statistics

• A. Carvalho,  F. Kurdahi,  S. Nassif.  IR and Thermal Estimation Tools, with Applications to the GUTS 1GHz Processor

• E. Malavasi,  E. Charbon,  B. Arsintescu,  W. Kao.  A Constraint Management System for IC Physical Design